A Parallel Turbo Decoding Message Passing Architecture for Array LDPC Codes
نویسندگان
چکیده
The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by interconnect and the storage requirements. Here, the proposed layout-aware layered decoder architecture utilizes the data–reuse properties of min-sum, layered decoding and structured properties of array LDPC codes. This results in a significant reduction of logic and interconnects requirements of the decoder when compared to the state-of-the-art LDPC decoders. The ASIC implementation of the proposed fully parallel architecture achieves throughput of 4.6 Gbps (for a maximum of 15 iterations). The chip size is 2.3 mm x 2.3 mm with a gate count of 787 K in 0.13 micron technology.
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